Intel Not Ruling Out PC133 SRAM Support

Welcome Guest. | Log In| Register | Membership Benefits

June 11, 1999 (3:31 PM EDT)

Intel Corp. is not ruling out a contingency plan to supportPC133 SDRAM if the new memory interface becomes the prevailing technology in the market, according to company president and chief executive Craig R. Barrett.

At the same time, Intel is blocking a rival from marketing a chipset that would support the memory interface.

While Intel has disclosed no plans to field its own PC133-compatible chipsets, "if it happens that PC133 becomes a preferred choice, Intel has lots of options for [creating] new memory bus lines in chipsets," Barrett said in an interview with EBN.

For months, the industry has speculated that Intel would add PC133 support in the event the new memory technology gains market acceptance, and Barrett's disclosure comes as the first hint that Intel might consider the interface. Intel's official roadmap still bypasses PC133, moving directly from PC100 SDRAM to Direct Rambus DRAM later this year.

Meanwhile, Intel sent a letter to a number of customers informing them that chipsets designed by Via Technologies Inc. using Intel's 133-MHz microprocessor bus violate terms of a license signed last fall by Intel and Via. The letter-which oddly enough was co-written by Via-pulls the rug out from under the Fremont, Calif., company's new Apollo Pro133 chipset, which features a 133-MHz frontside processor bus and support for the PC133 memory interface.

In the letter, which was obtained by EBN, Intel said it would not ask Via to recall the sample chipsets containing the 133-MHz frontside bus, but Intel "does not agree to any more of these samples being made or delivered" to customers.

Via stated in the letter that "it hopes that these steps will address any confusion that its sales and marketing efforts may have caused," and that it will "demonstrate the value of Via's products when it is appropriate to do so." Via could not be reached for additional comment.

While the licensing squabble and Barrett's comments raise questions, they shed little new light on the specifics of Intel's long-term main-memory plans.

Though he acknowledged the existence of what he called "contingency options," Barrett reaffirmed Intel's commitment to Direct Rambus DRAM as the industry's standard memory for next-generation PCs. And despite evidence pointing to a staggered introduction of the Camino chipset, Barrett said he expects Direct RDRAM and a corresponding Camino core-logic device to be unveiled in September.

As Direct RDRAM tracks into the market, component suppliers and PC makers alike believe it will initially serve high-end PC and workstation segments-systems generally defined as costing upwards of $1,500, and often more than $2,500. When they are introduced, Direct Rambus chips should carry a significant price premium over PC133 SDRAMs due to the fact that Rambus dice are as much as 25% larger, and because of the higher test and packaging costs associated with the new architecture.

PC133 is a follow-on to the PC100 SDRAM used in most PCs today. Because of its more evolutionary architecture, PC133 is expected to appear in a number of low-end systems.

Nevertheless, executives from Intel and from RDRAM's designer, Rambus Inc., Mountain View, Calif., said Rambus' higher overall performance will put the technology in a class by itself, and added that much of the early cost overhead will dissipate once Rambus chips enter volume production.

"PC133 may or may not gain acceptance in mainstream PCs, but it's not a competitor to Rambus as far as we're concerned," said Geoff Tate, Rambus' president and chief executive, speaking at an investment conference last week in San Francisco. "Even if it's 33% faster [than PC100 SDRAM], it's only a third as fast as Rambus."

However, Barrett said, if demand for PC133 is strong, Intel has the wherewithal to add support for the chip-in addition to backing Direct RDRAM. According to observers, if it chooses to, Intel can simply adapt the industry's PC133 open standard. The standard and associated chipset specs were drafted by a broad-based industry group, including IBM Microelectronics, which worked with Intel to develop the original PC100 standard.

Barrett also confirmed industry reports that new versions of the 810 chipset family could be used to support PC133. "That's only one of many options," he said. "There are all sorts of memory-bus-line approaches."

According to specifications released by Intel, the 810 core-logic chipset integrates the Intel i752 graphics core. As a separate discrete graphics chip, the i752 is the first Intel product to support a 133-MHz SDRAM frame buffer. But when integrated into the 810 chipset as a graphics core, the i752 doesn't have its own port to memory, meaning that it must connect through the 810's slower PC100 SDRAM interface.

However, analyst Robert Merritt of Semico Research Corp., Phoenix, said that in a future 810 chipset, Intel could offer PC133 memory support simply by activating an i752 port to the faster interface.

"It's easy to see an Intel migration in the 810 chipset to PC133," said Brian Folsom, member of the technical staff of chipset developer Poseidon Technology Inc., San Jose.

What's more, Intel this fall is expected to unveil a new version of the 810 chipset, the so-called 810e, which will add a 133-MHz frontside processor bus line and set up the possibility of adding a memory bus for PC133 SDRAMs, analysts said.

Intel for the first time this week confirmed the existence of the 810e and the 133-MHz frontside bus, but stressed that the new device will support only PC100 SDRAM.

Yet several of Taiwan's motherboard vendors said recently that their analysis of the 810e indicates the chipset is PC133-compatible. "Intel's denial that the 810e won't support PC133 is a policy issue but not a spec issue," said an executive at one of the island's largest board makers. "The chipset does support PC133."

Intel's 810e scenario also sets up a curious clocking mismatch between the 133-MHz frontside bus and the 100-MHz memory that fails to take full advantage of the higher MPU bus speed. In fact, in an integrated core-logic/graphics chipset such as the 810 family, the higher-speed PC133 interface would offer 1.06-Gbyte/s bandwidth, compared with only 800 Mbytes/s for PC100, according to Semico's Merritt.

This clock mismatch opens a window of opportunity for third-party chipset vendors able to pair the faster 133-MHz frontside bus and PC133 memory, observers said. It's an opportunity Via intends to exploit, and could explain why Intel used its clout to get the company to inform customers of the purported license violation.

The Intel spokesman would not comment on the contents of the letter it co-authored with Via, other than to say that it "addressed the confusion concerning the licensing agreement Via and ourselves signed last November."

According to reports, the letter was issued not long after Intel filed a lawsuit against Via charging the company with breach of contract. Intel retracted the suit the same day and said it had been filed in error. However, industry observers and Via itself believe the action was designed to intimidate third-party chipset suppliers. Intel denies the allegations.

"The implication was that it was about [the] 133-MHz [bus], which I believe," said Peter Glaskowsky, an analyst with MicroDesign Resources in Sunnyvale, Calif.

"There's no way that taking a licensed [component] and running it at a faster 133-MHz speed should mean that all of a sudden it's not licensed," he said. "But if there's something in the Intel technology [Via is] not complying with, then ... Intel has the right to make sure [the chipset] works with its microprocessors."

Industry observers speculated that Intel could have two motives for trying to bar Via from entering the PC133 market: Intel wants to make sure it gets there first, or it wants to derail potential competitors to Direct RDRAM.